Method of producing a high voltage PN junction

ABSTRACT

A PN junction having very low concentration gradients on both sides exhibits substantially increased breakdown voltages. A PN junction extending to the surface of a semiconductive body is formed by diffusing material of a first conductivity type into material of a second conductivity type in two stages: in the first stage, the surface concentration of impurity atoms is no higher than about 1016 per cc., and is always two to four orders of magnitude less than conventional junctions. In the second stage, the area of diffusion is smaller, so as to be surrounded by the area of said first stage diffusion, but concentration and depth are at normal levels, roughly 1017 - 1020. The higher the concentration is in the second stage, the greater the concentration difference between the two stages must be. Breakdown voltages of devices employing the junction of the invention are improved: planar transistors with BVcbo 1000 volts may be produced. Other properties of devices employing the junction of the invention are either not affected or are improved, and employment of the junction is essentially independent of other design parameters. The junction of the invention may be used in both active and passive devices, and is adapted for use in integrated circuits and for PN junction isolation. In dielectrically isolated integrated circuitry, a further improvement is achieved by diffusing into the oxide dielectric and polycrystalline matrix material in areas that will underlie leads, effectively burying the junction in these areas.

Kravitz [4 Nov. 18, 1975 METHOD OF PRODUCING A HIGH VOLTAGE PN JUNCTIONBernard L. Kravitz, Forest Hills, NY.

Assignee: Dionics, Incorporated, Westbury,

Filed: Nov. 15, 1973 Appl. No.: 416,171

Related US. Application Data Continuation-impart of Ser. Nos. 175,124,Aug. 26, .1971, abandoned, and Ser. No. 259,763, June 5,

1972, abandoned.

[75] Inventor:

US. Cl. 148/187; 148/186; 357/47 Int. Cl. H01L 21/22 Field of Searchl48/l.5, 186, 187;

OTHER PUBLICATIONS Magdo et al., Ultra High Speed Transistor, IBM Tech.Discl. Bull., Vol. 13, No. 6, Nov. 1970, pp. 1423, 1424.

Ghosh, P-EPI Transistor Having a Retarded Base Region, IBM Tech. Discl.Bull., Vol. 13, No. 6, Nov. 1970, p. 1740.

Primary Examiner-L. Dewayne Rutledge Assistant Examiner-J. M. DavisAttorney, Agent, or FirmJames J. Burke [57] ABSTRACT A PN junctionhaving very low concentration gradients on both sides exhibitssubstantially increased breakdown voltages. A PN junction extending tothe surface of a semiconductive body is formed by diffusing material ofa first conductivity type into material of a second conductivity type intwo stages: in the first stage, the surface concentration of impurityatoms is no higher than about 10 per cc., and is always two to fourorders of magnitude less than conventional junctions. In the secondstage, the area of diffusion is smaller, so as to be surrounded by thearea of said first stage diffusion, but concentration and depth are atnormal levels, roughly 10 10 The higher the con- ,centration is in thesecond stage, the greater the concentration difference between the twostages must be. Breakdown voltages of devices employing the junction ofthe invention are improved: planar transistors with BV 1000 volts may beproduced. Other properties of devices employing the junction of theinvention are either not affected or are improved, and employment of thejunction is essentially independent of other design parameters. Thejunction of the invention may be used in both active and passivedevices, and is adapted for use in integrated circuits and for PNjunction isolation. In dielectrically isolated integrated circuitry, afurther improvement is achieved by diffusing into the oxide dielectricand polycrystalline matrix material in areas that will underlie leads,effectively burying the junction in these areas.

9 Claims, 19 Drawing Figures U.S. Patent Nov. 18, 1975 Sheet 1 of33,920,493

U.S. Patent Nov. 18, 1975 Sheet 3 of3 3,920,493

METHOD OF PRODUCING I-IIGH VOLTAGE PN JUNCTION RELATED APPLICATIONSBACKGROUND OF THE INVENTION ing conductivity type materials are diffusedand, by

etching to form active devices, the junctions without protective oxideextend only to the edges of the bulk semiconductive material.

Planar devices have heretofore been limited to rela- 2 resist on theentire oxide surface, except the desired base region. Etching throughthe opening in this mask removes the SiO and exposes the underlyingsilicon. The wafer is now ready for the steps which will form the baseregion of the transistor (the body of the wafer will form the N-typecollecter). The first step is to deposit a controlled amount of P-typematerial, commonly boron, onto this exposed surface. A diffusion furnaceis typically used. For very accurate control of the deposition of theP-type material, it is possible to adjust the deposited concentration byuse of a wet oxidation which will serve to leach some of the boron awayfrom the Si and into the SiO By measuring sheet resistance after thisstep, the desired level of P-type impurities on the silicon surface canbe more precisely reached. Other methods are also known.

The next, step is to diffuse the P-type material from the surface of thesilicon into the body thereof, creating a P-type base region within theN-type collector region. A diffusion furnace is employed for thispurpose, and results in a collector-base PN junction being formedbetween the two regions. The concentration of P,-type material in thebase region is typically 10" 10 atoms per cubic centimeter, and thedepth of the diffusion is typically 6 microns. It will be noted thatthis junction I extends up to the single major surface of the wafertively low voltages because they break down due to cer- Formation of theemitter region follows, and involves similar steps. An oxide was grownover the base opening during the base drive-in diffusion and an emittervoltages, and are thus capable of higher voltage operation. They aremore reliable under normal conditions,

since they have a greater margin of safety under equiv-- alent biasingconditions. They may be operated'at higher line voltages, eliminatingthe need for voltage mask now defines an emitter area within the basearea.

The oxide in this area is removed by etching, and an N- atoms per cc.,and the depth of the diffusion is typically reducing equipment.Alternatively, with surface breakdown eliminated as a problem, geometrycan be changed to improve frequency characteristics, or bulk resistivitycan be lowered to improve saturation characteristics. I

A principal application of the present invention is in the constructionof planar transistors, either as discrete devices or as parts of anintegrated circuit. Understanding of the invention will be facilitatedby briefly reviewing typical prior art procedures for the production ofsuch devices. For the production of an NPN transistor, the startingmaterial will be a wafer of single crystal N- .type silicon or a layerof N-type epitaxial silicon grown on a N+type silicon base. The waferwill have a bulk resistivity of several ohm-centimeters (fl-cm) and anor mal N-type impurity concentration of about 10 10 (concentrationsreferred to herein, except for starting materials, are surfaceconcentrations, in atoms/cc). After lapping and polishing, or afterepitaxial layer deposition, a film of silicon dioxide (SiO is grown on amajor surface of the wafer by either low or higher temperature oxidationtechniques, steam being a common oxidant. For many applications, anoxide film thickness of about 6000 angstroms (A) is sufficient.

The surface geometry of the transistor more particularly the size andconfiguration of the base and emitter areas has been worked out inadvance in conformity with desired properties in the finished device,and results in the generation of masks for these areas.Photolithographic techniques are employed, in conjunction with theproper mask, to deposit an etch 4 microns. I

v The transistor is now complete except for making electrical contactthereto. Again, the oxide had been regrown over the emitter areas duringthe emitter diffusion, and yet another mask is now used to definecontact areas for the base and emitter terminals. When the oxide hasbeen etched from these areas, a metal such as aluminum is evaporatedonto the surface of the wafer. Still another mask is used to cover thedesired contact areas, and the metal in the uncovered areas is removedby etching. The collector contact may be on the top or bottom surface.In the latter case, it is formed by evaporating another metal, typicallygold onto the bottom surface of the wafer. Normal procedures are tomanufacture a large number of these devices on a slice of silicon and,after completing the steps enumerated above, cut or dice the slice intoindividual transistors.

A variety of problems are associated with the point where the leadcrosses the junction. These problems are different in different devicesand are not well understood, but are generally referred to aschannelling, surface inversions, MOS effects and the like. In essence,the voltage in the lead and its polarity induce a change in the behaviorof the junction near thesurface, which of course changes the behavior ofthe device. The magnitude of these problems is kept within acceptablelimits by spacing the base and emitter contacts sufficiently far apart,and increasing the thickness of the SiO layer. Increased spacing of thebase and emitter, however, requires that the chip itself be larger. Thisis undesirable since the larger the chip, the fewer chips will beproduced per wafer.

The present invention overcomes the lead-over-junction problems indielectrically isolated scmiconductive devices having high-voltagejunctions of the abovenoted type. Dielectric isolation is a well knowntechnique familiar. to those skilled in the art. Briefly, separatediscrete devices are produced from a single wafer and are separated fromeach other by dielectric material, generally SiO and are retained in amatrix of polycrystalline silicon or even glass. To produce suchdevices, a slice of single crystal silicon is first grooved in a desiredpattern to a desired depth to define discrete device areas on each chip.SiO is grown on the entire surface. Polycrystalline silicon is thenepitaxially grown on the SiO The slice is then turned over, and thesingle crystal surface is lapped down until the grooves cut in the otherside appear. The resulting slice comprises a plurality of tubs of singlecrystal silicon, each entirely surrounded by a layer of SiO and set in amatrix of polycrystalline silicon. Depending on groove geometry, thetubs may be isolated on the surface by just SiO or SiO andpolycrystalline material. Active devices are assembles in the silicontubs and leads are evaporated onto the surface. The polycrystallinesurface may be lapped or etched away to expose the tub bottoms forcollector electrode attachment, or the collector lead may be on the topsurface.

Dielectrically isolated devices may employ the highvoltage doublediffusion type junctions referred to hereinabove and they will,ordinarily, be subject to the same lead-over-junction problems thatconventional planar devices and circuits suffer from.

Before considering the efforts of prior workers to raise the voltagecharacteristics of planar devices, the applicable parts of the operationof a conventional planar transistor should be considered, and attentionis directed to FIG. 1. This is a typical transistor structure as couldbe produced by the above-enumerated processing steps. Regions ofdifferent conductivity type are labelled (it is to be understood thatNPN and PNP structures are substantially equivalent in operation, andeither may be employed). Thus the transistor of FIG. 1 comprises anN-type collector region 12, a P-type base 14 and an N-type emitter 16,collector-base junction 18 and emitter-base junction 20 defining thevarious regions. A layer of SiO 22 covers the surface of the deviceexcept for the base contact 24 and the emitter contact 26, both of whichare typically evaporated aluminum. A gold collector contact 28 isevaporated onto the bottom surface. For clarity the SiO layer 22 isshown as being of uniform thickness but, because of the variousre-growing and etching steps it actually has a stepped appearance. TheSiO layer 22 is commonly referred to as a passivation layer, because itprotects the sensitive PN junctions and passivates them against theharmful effects of moisture and surface contaminants.

[t is known that the maximum electric field for a particular voltage ona PN junction increases as the doping on either or both sides isincreased; while in general the breakdown voltage of a junction dependson the bulk resistivity of the lightly doped side, junctions heavilydoped on both sides are known to generate a substantial peak field evenat modest applied voltages, since the space charge will spread inrelation to the concentration on both sides. The main characteristic ofan electric field is, of course, that it accelerates charge carriers(electrons or holes). As the reverse voltage across a junction increasesthe electric field increases and the carriers are accelerated more andmore, until a point is reached where a single carrier colliding with asilicon atom causes a pair of carriers to be released. This pair itselfis accelerated and the process of carrier generation continues until itresults in avalanche breakdown of the junction. It is believed that themagnitude of the field and the distance over which it obtains are themain factors influencing the voltage at which avalanche breakdown willoccur. It is clear, however, that lightly doped, high resistivityjunctions create less of a field than heavily doped junctions, and areto be preferred in any high voltage device. Thus, typical high voltagedevices are diffused into high resistivity silicon, even though theyhave other voltage-limiting problems.

Each junction 18, 20 in transistor 10 has its own associated BV. Thevoltage across the collector-base junction 18, with the emitter open, BVand the voltage from collector-to-emitter with the base open, BV are theimportant ones; breakdown across the base-emitter junction (BV,,,,,,)invariably occurs at a lower level due primarily to the much heavierdoping level in the base.

A factor that may be significant in affecting surface breakdown voltageis the behavior of doping atoms during various oxide growing stepsinherent in the manufacturing process. Since surface boron incorporatesmore readily into SiO than into silicon, under oxidegrowing conditionssome boron is leached from the silicon surface into the growing oxide.Conversely, phosphorus segregates more readily into elemental siliconthan into the growing oxide, so that as the oxide grows, phosphorusaccumulates on the silicon side of the interface, the so-called snowploweffect. Thus the segregation coefficient to the impurity between theoxide and the silicon, and the time and temperature of the oxidation,all work to redistribute the impurities in the vicinity of the surface,modifying the bulk resistivity at the surface. The effect thereof underconditions of reverse bias may well be the creation of a lower voltagejunction, collector to base, which breaks down at a much lower voltagethan the bulk material would indicate.

The BV of a device can, of course, be increased by using a startingmaterial having a higher bulk resistivity, but this is often to thedetriment of other important parameters, such as frequency response andsaturation level. As a result, the bulk of the effort to increase BV ina silicon planar devices has been concentrated in the area of changingthe surface characteristics of the material near the collector-basejunction, in effect trying to block channels with so-called guard ringsor field relief rings. Some of these efforts are discussed below.

2. Prior Art The foregoing is all well known to those skilled in the artand is presented herein in summary form only to provide the necessarybasis for understanding of the present invention. A more detailedtreatment of the subjects discussed may be found in many standard texts,such as Warner and Fodemwalt (Editors), Inlegrated Circuits, Motorola,Inc. Semiconductor Products Div. (1965). The particular problemsassociated with junctions under SiO films are treated by Atalla et al.,Impurity Redistribution and Junction Formation in Silicon by ThermalOxidation, Bell Systems Technical Journal, July l960.

It is generally agreed that at the interface between a semiconductivebody and the overlying oxide film,

charges may be present or may be formed, which charges can move underthe influence of an electric field. This is referred to as a surfacecharge. As a result of the presence of such surface charges, so-calledinversion layer may be formed on the semiconductor surface below theinsulating oxide. The inversion layer has a conductivity type oppositeto the conductivity type of the underlying semiconductive material. Itis believed that such an inversion layer not only reduces breakdownvoltages but also, because it effectively increases PN junction surfacearea, increases capacitance, which is particularly undesirable in highfrequency devices.

To remove or reduce these surface charges and inversion layers, a fieldrelief ring may be employed. This is an annular metal layer placed overthe insulating oxide layer at the area of the PN junction, which layeris connected to a reference potential (usually one side of thejunction). Problems associated with field relief rings are that therings should be fully enclosed, and they must be insulated fromoverlying conductives U.S. Pat. No. 3,491,273 of Stiegler discloses afield relief electrode.

A guard ring is a different approach to solving the same problem. Aguard ring is in the semiconductive material and extends to the surface,but is spaced at a distance from the PN junction. The guard ring isgenerally of the same conductivity type as the underlying material, buthas a significantly higher charge carrier concentration. Thus, if thebulk material is P-type, the guard ring would be designated P+. Theconcentration of charge carriers in the guard ring is sufficiently highso that an inversion layer on one side or the other thereof isinterrupted. Drawbracks to this type of structure include the fact thatthey consume a lot of area, since if they are too close to the junctiona low breakdown voltage (between the base material and the ring) willresult. This is undesirable, particularly in integrated circuits.

Haenichen, U.S. Pat. No. 3,226,614 (1965) is typical of many patents inthis area. Briefly, the base region is extended in a thin surface regionhaving a higherresistivity than the bulk material on the base, therebyencouraging breakdown in the bulk rather than the surface. Thisintentional channel terminates in a ring of low resistivity material ofthe opposite conductivity type. This is alleged to prevent breakdownthrough induced channels. However, no figures are given on what BV isachieved with this geometry.

In Tremere, U.S. Pat. No. 3,338,758 (1967) a PNP device is disclosedwherein a lightly doped out-diffused '(P-) layer is provided across theentire'surface, and a raising of the effective breakdown voltage of asilicon planar diode from 600 to l 100 volts, by the interposition of aring containing substitutionally active ions in interstitial positions.Martin et al., U.S. Pat.

No. 3,515,956 (1970) employs ion implantation means to dope a very highresistance (9 ,000-1 1,000Q-cm) N- 'type starting material. It is notedthat any device employing such material could theoretically be expectedto have a BV of thousands of'volts. Such material is never used inconventional devices, however, because of the deleterious effect onother parameters. But the device disclosed by the patentee is by nomeans conventional, including as it does a junction V2 inch in diameter.The passivated device is first provided with the 16 inch P-type regionof 0.01 Q-cm and then an even wider area is irradiated with kilovoltboron ions to implant 10 ions per cm Annealing follows. In one instancecited leakage current is reduced while BV is unaffected and in anothercase BV is raised to l 100 volts but leakage current is not affected.The former is attributed to an inversion layer and the latter to anaccumulation layer, but why two different results are produced by thesame process is not disclosed. The leakage currents reported are in themicroampere range, some 3- 4 orders of magnitude larger than can betolerated in conventional devices, where such currents are normallymeasured in nanoamperes.

In considering this patent, it is to be noted that ion implantationproduces interstitial impurities (i.e. impurities located within thecrystal lattice between lattice sites), whereas diffusion producessubstitutional impurities (i.e. impurities occupying lattice sites). Anyinterstitial atoms inherently strain a lattice, and a lattice straininherently increases leakage currents. Thus, the second irradiationmentioned at a lower level than the first, would appear to amelioratethe problems created by the first, in producing a gradually strainedinstead of a sharply strained lattice. Further, it is apparent that thistreatment merely increases the resistance of the material, resulting inthe same leakage current at a higher but still disappointing voltage,since BV for 9l1,000Q/.cm N-type material should be several thousandvolts. 1

While the present invention is concerned with planar rather than mesatechnology, the patent of Blicker et al., No. 3,427,515 is of interestbecause of the concept of the symmetrical junction described therein. Inparticular, it is pointed out that in prior art high-voltage transistorsthe collector-base junction includes a collector region of very lowimpurity concentration and corresponding high resistivity, and adiffused base of high impurity concentration, so the junction is veryabrupt. This produces a high electric field under conditions ofreverse'bias, and the junction breaks down readily. The patentees teachthe formation by epitaxial rather than-diffusion techniques ofsub-regions of the junction, these base and collector regions having thesame thickness and preferably the same concentration (a factor of 3being the limit for concentration differences). This symmetricaljunction exhibits a 50% lower field strength for a given reversevoltage, and the breakdown voltage is thus effectively doubled. Asdescribed by Blicher et al, the method is not applicable to planardevices.

British Pat. No. 1,153,495 of Lamming (1969) discloses a double-diffusedbase region adapted to overcome the so-called base push-out or emitterdip" effect. Specifically, during emitter diffusion the collector-basejunction is pushed farther into the collector region in the area belowthe emitter. This can give rise to poor electrical characteristics,particularly in high frequency planar transistors, where very narrowbase widths are required. Starting with N-type silicon of 2 X 10 donorconcentration, the patentee first diffuses boron to a surfaceconcentration of 2 X 10 over a wide area which forms the junction at itsperiphery, and then diffuses boron over a smaller area to a surfaceconcentration of 10 the smaller area being surrounded by the largerarea. Emitter diffusion follows,

7 and has the effect of driving the second base zone into the first basezone below the emitter, but does not move the locus of the junctionformed by the first zone. The patentee does not comment on BV but thereare two reasons why this would be the same orlower than in conventionaldevices. At the high base impurity concentration disclosed (10 it isnecessary that the lower concentration zone be at least four orders ofmagnitude less for increased breakdown voltages to be observed. Further,in the area below the emitter where the second zone is'disclosed-asreaching the original junction, there will be a very steep concentrationgradient, and this tends to lower BV The recent patent of Davidsohn, No.3,716,425 (1973 is also of interest in disclosing simplified diffusionmasks which include adjacent tubs of single crystal silicon and thedielectric and matrix material therebetween. 1

While most of the prior art patents are devoid of actual figures for BVunder defined conditions, it is believed that highest voltage planardevices currently available are rated at about 300-400 volts, and suchdevices are sufficiently expensive to make their use uneconomical,except in miltary and space application.

OBJECT OF THE INVENTION It is a general object of the present inventionto provide a planar, diffused PN junction having a breakdown voltageapproaching, or equal to the bulk breakdown voltage of the material.

Another object of the invention is to provide diffused, planarsemiconductive devices having breakdown voltages approaching or equal tothe bulk breakdown voltage of the material.

A further object of the invention is to provide diffused, planarsemiconductive devices having high breakdown voltagesand wherein otherdevice parameters are not adversely effected.

Still another object of the invention is to provide a planar, diffusedPN junction of high breakdown voltage which is useful in making highvoltage diodes, resistors, transistors and integrated circuits.

Another object of the present invention is to provide planar,dielectrically isolated semiconductive devices having high voltage PNjunctions wherein the leadover-junction problems are substantiallyreduced or eliminated. v I

A still further object of the present invention is to provide planar,dielectrically isolated semiconductive devices, having high voltage PNjunctions, which devices are smaller than similar devices heretoforeavailable.

Various other objects and advantages of the invention will become clearfrom the following description of embodiments thereof, and the novelfeatures will be particularly pointed out in connection with theappended claims.

SUMMARY OF INVENTION In essence, the foregoing objects are achieved byproviding a planar PN junction with a lowconcentration gradient on bothsides thereof. This is accomplished by diffusing the starting materialin two stages: the first stage is from 0.5 mil to 1 mil greater inradius than the second stage, 'and may be the same depth but ispreferably of greater depth than the second stage. The averageimpurity'concentration in the first stage is two to four orders ofmagnitude less than the concentration thereof in the second stage,.andis generally no higher than 10 atoms/cc. The second stage is the normalbase diffusion which, depending on the device design, will have animpurity concentration from low (10") to high (10 In the former case,the first stage diffusion would be to no more than I0 or two orders ofmagnitude difference, and in the latter case the limit would be 10 orfour orders of magnitude difference. The end in view is to produce ajunction having low concentration gradients on both sides, it being hereassumed that the starting material is of nominal bulk resistivity (30-IOOQ-cm) established with an opposite conductivity impurity of about 10In transistor manufacture, the second stage diffusion referenced here isa conventional base region, and collector and emitter regions areconventional in every respect, as are the SiO passivating layer and themetallic contact pads. Thus', a transistor in accordance with theinvention is made by employing all of the conventional steps, plus anadditional base diffusion, slightly larger in area and considerably lessconcentrated in impurities, than the conventional base. The same conceptis employed to increase the breakdown voltage of an integrated circuitresistor, a diode and a pair of PN junctions used for electricalisolation. Using the same double diffusion technique on the base region,a deeply diffused emitter may be provided to produce a transistor with acorrespondingly narrowed base and increased frequency response whilestill retaining higher voltage characteristics than normal. Further,this technique can be employed with lower-than-normal bulk resistivitystarting materials, with the production of devices having normalbreakdown voltages but better saturation characteristics.

When applied to dielectrically-isolated (or DI) integrated circuitry,the present invention can also overcome the above-mentionedlead-over-junction problems if the added diffusion step is carried outin an area that extends to or beyond the boundary of the device, atleast in such areas as underlie the leads which cause the problem. Ineffect, this buries the junction underlying the lead on the edge of thedevice and keeps it away from the surface. As a practical matter, it isdesirable to extend the diffusion zone a short distance into thesurrounding SiO or polycrystalline material, because of tolerances in DIprocessing techniques. 50, if the mask is cut to allow diffusion intothe polycrystalline silicon of 0.5 mil or more, one is assured that thediffused zone will cover the desired areas. While the SiO is subjectedto diffusion, the extent that dopant actually is diffused into it issmall, and unsufficient to change its dielectric properties.

With conventional construction, the collector contact on a transistor(or the cathode on a diode) must be spaced from the junction asufficient distance so that spreading of the space charge from thejunction does not affect operation. With the present invention, whereinthe high voltage diffusion zone extends to the edge of the SiO tub, thespace charge can spread down but not out, and contacts can be closer andthe overall size of the chips reduced. For example, a conventionaltransistor that required a 40 by mil chip was redesigned employing thediffusion zone of the present invention on a 30 by 51 mil chip. Thisreduction in device size permits almost twice as many chips to beproduced on a'wafer, and a much better yield, in terms ofdevices-per-wafer, is achieved.

. 9 THE, DRAWINGS Reference will herein be made to theaccompanyingdrawings wherein:

FIG. -1 is a perspective view, in section, of a typical prior art planardiffused transistor;

FIG. 2is an elevation,,-insection,' of a tr'ansistorfin accordance withthe presentinvention; i"

FIG. 3 is a plot of diffusion c'urves'(d'i stance from sur- I face'VsCimpurity concentration) for conventional'coL' lector base junctionsand said junctions manufactured in accordance with the presentinvention;

FIG. 4A-4F illustrate the steps involved in producing the structure ofFIG. 2;

FIG. 5 is a sectional e'levatio'nof an integrated circuit resistor inaccordance" with the invention; isolation structure has been left outfor clarity,

FIG. 6 is a plot of current vs. voltage for conventional resistors andthe resistor of FIG.; 5;

FIG. 7 is asimplified, sectionalelevationof a portion of an integratedcircuit illustrating PN junction high voltage isolation in accordancewith the invention;

FIG. 8 is a schematic sectional elevation of a highfrequency, narrowbase transistor in accordance with theinvention; I j

FIG. 9 is a voltage-current plot for conventional transistor junctionsand transistor junctions made in accordance with the present invention;

FIG, 10 is a voltage-current plot for a junction in a transistor made inaccordance with the present invention; I j v FIG. 1 l is a plan viewschematically showing adielectrically-isolated diode made in accordancewith the present invention;

FIG. 12 is across-sectional elevation taken along line DESCRIPTION OFEMBODIMENTS I g Referring now to FIG. 2, a diffused planar transistor ofthe NPN type is shown. Referring to FIG. 4A, N-' type starting material32, a slice'of single crystal silicon .having a bulk resistivity of30-100Q-cm, is employed (it is to be understood that FIG. 2 and FIGS.4A-4F ,show a single device, but that several thousand identical devicesare produced in a single slice simultaneously). Preparation of the slideis conventional: it

must'be lapped and polished unless it is epitaxial silicon. In thelatter case, it is'noted that the epitaxial layer must be sufficientlythickto support the intended voltage The wafer is then oxidized byeither low or high 'temperature oxidation techniques to provide an SiOlayer 34 on one surface. Again, the thickness of layer 34 must besufficient to support the intended voltage. About 12,000 A is requiredin many instances where 6,000 A would be sufficient on a conventionallow voltage device. After the layer 34 is grown thefirst d iffu-l sionmask is employed to cut an opening 36 layer 34' anddeposit a P-typematerial such as bioro r onto the l0 surface and diffuse it into P-baseregion 38 (FIG. 4B).

, This may be termed the high voltage diffusion.

The geometry of opening38 depends largely on the conventional baseregion 44 (FIG. 2) that is being made into a high voltage device. First,it is to be noted that while square geometry may be employed, round ispreferred since there are no corners to act as electric fieldconcentration points. The siie of opening 36 will,

ofcourse, determine the size of region 38. From the standpoint ofmaterial economy, it is desirable that x, the difference inradii'between the high-voltage region 38 and conventional'base region 44be as small as possible. This may be termed the lateral field distance.However, the limits of resolution 'of current photolithographictechniques make a value of x of less than 0.2

milquestionable in terms ofreproducibility. For maximum BV, on the otherhand, x should be large. It has been found, however, that for values ofx greater than I mil the degree of improvement in BV is small comparedto the cost" of using significantly more material. Thus,'for practicaldevices of substantially conventional geometry, values..ofx fromjabout0.5 mil to about 1.0 mil are preferred. 1 1

In the deposition and diffusion 'of the P-type material into region 38,the depth and average concentration of impurities are important, but themeanj s .by which they are achieved is not critical. A typicaldeposition of boron may involve treatment at 920C for 15. minutes in aflow of nitrogen-diluted diborane. Then, in a second furnace, oxidationin steam is carried out while including a sample forlater measuringsheetresistance to achieve the exact surface concentration of desiredboron (as noted hereinabove, boron tends I to be leached from thesilicon into the oxide due to differential diffusion and seg regationcoefficients). The boron is then driveninto the surface in a diffusionfurnace by heating, typically at 1 C for a period of 15 hours in anatmosphere of nitrogen. 'Typical results are a diffu;

this discussed herein-below in connection withFIG. 3.

Duringithe oxidation and diffusionsteps the oxide regrows 40 (FIG. 4C)over opening '36.,The second mask is now employed to etch anotheropening 43 (FIG. 4D) in oxide 40, corresponding to the conventional baseregion, and depositing and diffusing additional boron therein to formbase region 44. Techniques may be the same as described-above, butcontrolled to produce the higher desired concentration and (as? shown inFIG.'2 and FIGS. 4D-4F) -a lesser depth. Generally the difference indepth y in FIG. --2) between thehigh voltage region 38 and theconventiorial base-44 will-be small, (as shown) but it inay also be azero or'a negative value under certain circumstances, as set forth morefully be,- low. It is important to note that the line'identified as 46between regions 38 and 44z-in FIG. 4D is not a PN junction, but ratherdefinesthdP-P boundary or transition zone between areas "of differentconcentration but similar conductivity" type. 4 t A During the oxidationand diffusionused to produce base 44, oxide. 48 regrovis over the baseopening 42 (FIG. Followin'g the same procedures as outlined before,aneniitter mask is used to etch another opening 1 1 addition of anemitter pad 54, a base pad 56 and a collector pad 58 (FIG. 2) the deviceis complete.

The mechanism by which devices produced in accordance with the presentinvention achieve a BV approaching or equal to the breakdown voltage ofthe material can only be theorized and the following comments arebelieved to be relevant. Attention is directed to FIG. 3, which is aplot of impurity concentration (C) versus distance from the surface (X)after the diffusion step. The dotted line A represents the impuritylevel in the bulk material (phosphorus for the N-type material describedhereinabove). Curve B corresponds to a conventional base diffusion, withan average surface impurity level of 10" boron atoms per cc.Concentration drops with distance from the surface until curve B crossesline A; this is the point x where the conventional PN junction isformed, because on one side thereof P-type impurities predominate, andon the other side N-type impurities are in the majority. Curve Crepresents the high voltage diffusion step of the present invention. Itis to be noted that the additive effect of the two diffusions is minimalin the heavily doped region because of the very low level (three ordersof magnitude less) of the first diffusion. For example, if the seconddiffusion is at a level of 5 X and the first is l X 10 the highestconcentration possible would be 5.001 X l0". Thus, the high voltagediffusion does not materially effect the properties of the base regionin the high concentration areas. Curve C starting with a surfaceconcentration of 10' intersects line A considerably farther into thematerial than Curve B, although this is not at all a necessity. Moreimportant, it is believed, the slope of Curve C is much less at thepoint x than the slope of Curve B at x Thus, the impurity concentrationin the vicinity of the junction is much more gradually changing than isthe case in a conventional junction. It is felt that this very gradualchange from N to P type conductivity is at least partly responsible forthe high voltage characteristics of junctions manufactured in accordancewith the present invention. It, at least, appears to be consistent withthe theory that a junction lightly doped on both sides creates less of apeak field at a given reverse bias than a heavily doped junction.Further, it is compatible with standard planar technology and results inoxide-passivated junctions.

FIG. 5 shows an integrated circuit resistor manufactured in accordancewith the present invention. A conventional resistor of this type wouldinclude a heavily doped P region 60 in the bulk N material 62 of theintegrated circuit. A layer of oxide 64 insulates a pair of conductors66, 68 connected to either end of P-type region 60. Such a resistorwould have current-voltage characteristics shown by Curve A in FIG. 6.By diffusion of a P zone 70, of two to four orders of magnitude lowerconcentration than region 60, breakdown is raised to the level shown inCurve B of FIG. 6. The lighter doping inherent in the P" zone has littleor no affect on resistor value.

The use of PN junction isolation is a common expedient in themanufacture of integrated circuits. A pair of junctions, back-to-back,is employed'to isolate active devices, each junction forming the edge"of one of the devices. FIG. 7 shows such an arrangement in simplifiedform: epitaxial N-type silicon is deposited on a P- type substrate 70,and active device regions 72 are formed by diffusion of P-type material74 therebetween. By first applying a high-voltage diffusion inaccordance with the present invention, the P regions 76 12 are formed,increasing the insulating capacity of each pair of junctionssubstantially.

It should be appreciated that the method of the invention is applicableto raising the voltage characteristic of an entire slice of integratedcircuits, with the single additional operation of a high-voltagediffusion. Thus, an additional mask is required and defines the areasfor high-voltage diffusion for transistors, diodes and resistors. Asingle deposition-diffusion cycle establishes the high voltage junctionsfor all devices on the slice.

As set forth hereinabove, the high-voltage diffusion of the invention iscarried out prior to the normal diffusion. This procedure can bereversed providing that account is taken of the fact that diffusion of apreviouslyestablished region continues during a subsequent diffusion. Anormal base region will expand during a subsequent high voltagediffusiomjust as a high voltage region will diffuse further during asubsequent normal base diffusion. Mask geometry and diffusion cyclesmust thus be corrected so as to achieve the proper impurityconcentrations and depths. The two steps may be consideredinterchangeable with this qualification.

With the capability for high voltage planar diffused junctionsestablished, it will be appreciated that in some instances it will bedesired to sacrifice the higher breakdown voltage in favor of improvingsome other device parameter. A very simple example of this is to use astarting material of lower bulk resistivity. Employing the invention inthis situation will maintain BV at the previous normal level but willimprove the saturation characteristics. Another example is thehigh-frequency transistor 78 shown in FIG. 8. This comprises an N-typecollector region 80, a P high-voltage region 82, a normal base region 84the same depth as region 82 (i.e. y 0) and a relatively deeply diffusedemitter 86. The latter provides a very narrow base width, thus improvingthe alpha cut-off frequency, while maintaining BV and BV at theconventional level. Normally, narrowing the base-width to a similarvalue would result in an undesirably low BV It will be noted that theconcentration gradients at the junction between regions and 84 will besteeper on the base side, which will tend to lower BV While it has beenstated that processing in other than the high-voltage diffusion isconventional, it will be appreciated that certain changes are necessaryto produce a high-voltage device. In particular, the thickness of thepassivating layer of SiO must be sufficient to handle the highervoltage. Similarly, the size, thickness and separation of the contactpads must be sufficient for the high voltage.

Understanding of the invention will be further facilitated by referringto FIGS. 9 and 10, which are both voltage-current curves for a junctionin a transistor. FIG. 9 has a solid-line curve for a transistor having abreakdown voltage of about 200 volts. It will be noted that there is arise in the leakage current at about volts, which is of courseundesirable. It is believed that this rise in leakage current is due toone of the aformentioned surface phenomena caused by current in the leadeffecting behavior of the junction at the cross-over point. A similartransistor with a double-diffused base region will exhibit an increasedbreakdown voltage, up to about 400 volts as shown by the dotted line inFIG. 9. However, the increase in leakage current at about 100 volts isessentially unchanged, compared to the transistor not so treated. If asimilar transistor is de- 13 signed with the high-voltage diffusion zoneextending to the side of the device in those areas underlying theappropriate leads, however, the voltage-current curve shows no increasein leakage current in the entire operating range (i.e. up to 400 volts),as shown in FIG. 10.

In applying the invention to the production of highvoltage integratedcircuits, it is advantageous to utilize the technique known asdielectric isolation, since structures employing this type of isolationinherently possess a much higher voltage capability than circuits usingPN junction isolation. A dielectrically isolated integrated circuitcomprises a plurality of single crystal silicon cups or tubs embedded ina polycrystalline silicon matrix, each tub having an oxide coatingbetween the embedded surfaces and the matrix material. High voltageactive and passive devices are fabricated in the tubs as hereinabovedescribed, with suitable interconnections forming the complete circuit.The invention is not used in the isolating function on such devices,since PN junctions are not involved.

Thus, with DI chips, the geometry of the mask used in the high-voltagediffusion step is changed so that the area of diffusion extends to orthrough the sides of the device in those areas underlying the leads. Inpractice, the mask is generally enlarged to cover an even greater area,because imprecision in manufacturing would be likely to reduce yield ifthe enlarged area extended only under the leads. Further, on many chipsthe neighboring chips on the wafer are usually symmetrically arranged,and in these circumstances it is possible to carry out the high voltagediffusion on a large number of devices simultaneously through a singleslit-type mask opening covering a large number of devices or chips. Sucha mask is considerably more economical than one with a separate openingfor each diffusion zone.

FIGS. 11 and 12 are top and cross-sectional views, respectively, of adiode constructed in accordance with the present invention. Adielectrically isolated slice is produced in accordance withconventional and wellknown techniques which have been summarizedhereinabove. The result is a matrix of polycrystalline silicon 90containing a plurality of single crystal silicon tubs 92, (one shown)each separated from the polycrystalline material by a layer of SiO 94. Alayer of SiO 96 also covers the entire top surface of the chip exceptwhere openings 98 have been etched for the attachment of anode andcathode leads, 100 and 102 respectively. In the manufacture of thedevice of FIGS. 11 and 12, the first diffusion step is carried out byetching an opening in the overlying SiO through a suitable mask, in theoutline indicated by dotted line 104 in FIG. 11. It will be seen thatthis opening extends beyond the SiO and into the polycrystalline matrixon three sides of the device 12. It is believed to be desirable to keepthe junction away from the surface whereever possible. As noted above,making the opening generally larger increases yield. Presuming that thetub 92 is N-type material, a P-type impurity is diffused through opening104 to form a P zone 106 (FIG. 12), the minus sign indicating aless-than normal concentration of P-type impurity atoms, generally twoto four orders of magnitude lower than the conventional concentration,and no higher than about After the initial diffusion described above,further processing is conventional: the surface oxide is regrown, a newopening is etched therein through a conventional mask and diffused toform a P-type region 108 of normal concentration, the oxide is regrownand etched for the lead openings 98, and leads are evaporated onto thesurface through a final mask (more commonly, aluminum is evaporated ontothe overall surface and the leads are patterned by etching through amask). The wafer is then diced into individual chips for furtherprocessing.

Construction of a dielectrically isolated transistor in accordance withthe present invention is illustrated in FIGS. 13 and 14. The startingmaterials may be the same as previously described, but of course thegeometry will be different, i.e. a polycrystalline silicon matrix havingtubs 92 of single crystal silicon embedded therein and insulated fromthe matrix and neighboring devices by a layer of SiO 94. The Si0 acrossthe bottom of a tub may be lapped away for attachment of a collectorelectrode 110, as seen in FIG. 14, but much more commonly the collectorwill also be on the top surface, as seen at 124 in FIG. 13.

As in the previously described embodiment, it is preferred that thehigh-voltage diffusion step be the first (this is so because bydiffusing through successively smaller mask openings, a step" pattern isintroduced in the regrown oxide covering layer 96, as shown in FIG. 14.The high-voltage base diffusion zone is shown in dotted outline 112 inFIG. 13, and results in a diffused zone 114 (FIG. 14) extending into thematrix material under both the emitter and base leads, 116 and 118respectively. The collector-base junction thus terminates on the edge ofthe device and does not extend to the surface, except on one edge remotefrom the leads. The impurity level of the diffusion is the same aspreviously described.

A conventional base region 120 and a conventional emitter 122 arediffused following known procedures, and leads 116, 118 are evaporatedonto oxide surface 96.

Relative impurity concentrations in the device may be explained asfollows, presuming the basic silicon 92 to be N-type. Emitter 122 willbe N, base 120 will be P, and beyond the boundary of the device zone 34will be P to the extent that it is in fact diffused. If it is desired tohave the collector contact on the top surface of the device, an N zone124 may be diffused therein, as shown in dotted line in FIG. 13.

The present invention is also applicable to devices incorporated intoair-isolated monolithic circuits. More particularly, the presentinvention may be applied with good results in the method for producingair-isolated circuits described in my US. Pat. No. 3,559,283 issued 2Feb. 1971 and in US. Pat. No. 3,680,205 issued 1 Aug. 1972, bothassigned to the same assignee as the instant application. In thesecases, the techniques of dielectric isolation are employed to increaseyields and reduce costs, with an etch step removing the polycrystallinematrix material to produce air-isolated circuits covered with SiO It hasbeen stated hereinabove and it is well recognized in the industry thatconductivity types are interchangeable, i.e. that a PNP device is thefull equivalent of an NPN device of the same geometry, dopant levels,etc. Nevertheless, in terms of cost, availability and general degree ofcommercial usage, NPN devices have been favored, it is believed becauseof manufacturing difficulties and reliability problems with PNP devices.The present invention has the same effect on PNP devices as it does onNPN devices; raising of the voltage characteristics makes the otherproblems of PNP construction more tractable, however, and it is feltthat the invention may find even broader application in this area.

Examples A 2N9l8 transistor typically has BV 18 volts. When treated withahigh voltage diffusion in accordance with the invention (x 0.5 mils, CB atoms/cc and a depth of 2 microns), BV 28 volts.

Starting with 40Q/cm material, a conventional transistor measured BV 220volts; the same geometry and procedures with a high voltage diffusionyielded a device with BV 800 volts.

Repeating the above procedure with 800/cm starting material raised BVc oto 900 volts in preliminary experiments. I

In all of the foregoing examples, other device properties were notaffected. Gain and frequency are controlled by the normal base andemitter diffusions and the high voltage diffusion has no effect thereonsince the high voltage diffusion can be made equal in depth to the base.Gain factors ranged from to 250 depending on the device. The gainbandwidth product (f,) ranged from 30 to 300 Mhz. The capacitance perunit area is unaffected since it is generally a function of resistivityon the lightly doped side.

Various changes in the details, steps, materials and arrangements ofparts, which have been herein described and illustrated to explain thenature of the invention, may be made by those skilled in the art withinthe principle and scope of the invention as defined in the appendedclaims.

What is claimed is:

1. In the construction of diffused, planar semiconductive devicesincluding the diffusion of one conductivity-type material into a body ofsemiconductive material having a concentration of the oppositeconductivity type impurities of less than about 10 atoms/cc, thereby toform a PN junction extending to a surface of 16 diffusing a base regionof opposite conductivity type impurities within said body to establish acollectorbase PN junction reaching a major surface of said body, saidbase region comprising first and second zones;

said first zone entirely surrounding said second zone on said surface;diffusing said first zone for a time sufficient to establish a surfaceconcentration of opposite conductivity impurities of less than about l0atoms/cc;

diffusing said second zone for a time sufficient to establish a surfaceconcentration of opposite conductivity impurities two to four orders ofmagnitude higher than said first zone; diffusing an emitter region offirst conductivity type impurities within said base region to establishan emitter-base PN junction reaching said major surface; and I coveringat least said exposed junctions with a passivating oxide film andattaching conductors to said respective collector and emitter regionsand to the second zone of said base region.

5. The method as claimed in claim 4, wherein said diffusions are carriedout for sufficient time to establish the concentration of oppositeconductivity impurities in said first and second zones within the rangeof IO 10 atoms/cc and 10 10 atoms/cc, respectively.

6. The method as claimed in claim 4, wherein said first stage diffusionis carried out so as to extend besaid body, the improvement comprisingdiffusing said I one conductivity impurity in interchangeable first andsecond stages, said first stage being carried out for sufficient time toestablish a concentration of less than about l0 atoms/cc, whichestablishes said junction, and said second stage diffusion being withinan area entirely surrounded on said surface and within said body by saidfirst stage diffusion and being carried out for sufficient time toestablish an average impurity concentration of said one conductivitytype of from two to four orders of magnitude greater than in said firststage diffusion.

2. The method as claimed in claim 1, wherein the bulk concentration offirst conductivity type impurities in said material is 10 l0 atoms/cc,and said first and second stage diffusions are carried out forsufficient time to establish average surface concentrations of said oneconductivity-type impurity of 10 l0 atoms/cc and 10" 10 atoms/ccrespectively.

3. The method as claimed in claim 1, wherein said first stage diffusionis carried out so as to extend beyond the periphery of said second stagediffusion on said surface by a distance of between 0.2 mils and 1 mil.

4. The method of producing a diffused, high voltage planar transistor ina semiconductive body having impurities of a first conductivity type ina bulk concentration of 10 10' atoms/cc comprising:

yond the periphery of said second stage diffusion on said surface by adistance of between 0.2 mils and 1 mil.

7. In the construction of dielectrically isolated, diffused, planarintegrated circuitry wherein discrete bodies of single crystalsemiconductive material are embedded in a polycrystalline or amorphousmatrix with an insulating oxide layer therebetween, and including thediffusion of one conductivity type material into a body ofsemiconductive material having a concentration of the oppositeconductivity type impurities of less than about 10 atoms/cc, thereby toform a PN junction within said body, followed by establishing an oxidefilm on a major surface of said body and connection of metallic leadsoverlying said film to opposite sides of said junction, the improvementcomprising diffusing said one conductivity type impurity ininterchangeable first and second stages, said first stage being carriedout for a time sufficient to establish an impurity concentration of lessthan about l0 atoms/cc, which establishes said junction, said firststage diffusion extending into said oxide layer beneath at least thelead to be connected to that side of said junction, said second stagediffusion being within an area entirely surrounded on said surface bysaid first stage diffusion and being carried out for a time sufficientto establish an average impurity concentration of said one conductivitytype of from two to four orders of magnitude greater than in said firststage diffusion.

8. The method as claimed in claim 7, wherein the bulk concentration offirst conductivity type impurities in said'material is 10 l0 atoms/cc,and said first and second stage diffusions are carried out forsufficient time to establish average surface concentrations of said oneconductivity-type impurity of IO l0 atoms/cc and 10" 10 atoms/cc,respectively.

9. The method as claimed in claim 7, wherein said first stage diffusionis carried out so as to extend beyond the periphery of said second stagediffusion on tion material at least 05 mils.

Tg ggi UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.3 ,929 Dated Nov. m 19 75 Invcncor(s) Bernard L. Kravitz It: iscertified that error appears in the above-identified patent z ad thatsaid Letters Patent: are hereby corrected as shown below:

Col. 'l,1.ine 31: "'are should be --as-;

Col. 3,line 24: "assembles" should be --assembled- Col. 6,1ine 22:delete "a'Y (second occurrence);line 34:

"Blicker" should be -Blicher--;

Col. 16, line 65: "10 should be "10 Signed and Sealed this thirteenthDay of April1976 [SEAL] A nest:

RUTH C. MASON Arresting Offiter C. MARSHALL DANN (mnmissium'ruflau'r'zls and Trademarks

1. IN THE CONSTRUCTION OF DIFFUSED, PLANAR SEMICONDUCTIVE DEVICESINCLUDING THE DIFFUSION OF ONE CONDUCTIVITY-TYPE MATERIAL INTO A BODY OFSEMICONDUCTIVE MATERIAL HAVING A CONCENTRATION OF THE OPPOSITECONDUCTIVITY TYPE IMPURITIES OF LESS THAN ABOUT 1015 ATOMS CC, THEREBYTO FORM A PN JUNCTION EXTENDING TO A SURFACE OF SAID BODY, THEIMPROVEMENT COMPRISING DIFFUSING SAID ONE CONDUCTIVITY IMPURITY ININTERCHANGEABLE FIRST AND SECOND STAGES, SAID FIRST STAGE BEING CARRIEDOUT FOR SUFFICIENT TIME TO ESTABLISH A CONCENTRATION OF LESS THAN ABOUT1016 ATOMS CC, WHICH ESTABLISHES SAID JUNCTION, AND SAID SECOND STAGEDIFFUSION BEING WITHIN AN AREA ENTIRELY SURROUNDED ON SAID SURFACE ANDWITHIN SAID BODY BY SAID FIRST STAGE DIFFUSION AND BEING CARRIED OUT FORSUFFICIENT TIME TO ESTABLISH AN AVERAGE IMPURITY CONCENTRATION OF SAIDONE CONDUCTIVITY TYPE OF FROM TWO TO FOUR ORDERS OF MAGNITUDE GREATERTHAN IN SAID FIRST STAGE DIFFUSION.
 2. The method as claimed in claim 1,wherein the bulk concentration of first conductivity type impurities insaid material is 1013 - 1015 atoms/cc, and said first and second stagediffusions are carried out for sufficient time to establish averagesurface concentrations of said one conductivity-type impurity of 1014 -1016 atoms/cc and 1017 - 1020 atoms/cc respectively.
 3. The method asclaimed in claim 1, wherein said first stage diffusion is carried out soas to extend beyond the periphery of said second stage diffusion on saidsurface by a distance of between 0.2 mils and 1 mil.
 4. The method ofproducing a diffused, high voltage planar transistor in a semiconductivebody having impurities of a first conductivity type in a bulkconcentration of 1013 - 1015 atoms/cc comprising: diffusing a baseregion of opposite conductivity type impurities within said body toestablish a collector-base PN junction reaching a major surface of saidbody, said base region comprising first and second zones; said firstzone entirely surrounding said second zone on said surface; diffusingsaid first zone for a time sufficient to establish a surfaceconcentration of opposite conductivity impurities of less than about1016 atoms/cc; diffusing said second zone for a time sufficient toestablish a surface concentration of opposite conductivity impuritiestwo to four orders of magnitude higher than said first zone; diffusingan emitter region of first conductivity type impurities within said baseregion to establish an emitter-base PN junction reaching said majorsurface; and covering at least said exposed junctions with a passivatingoxide film and attaching conductors to said respective collector andemitter regions and to the second zone of said base region.
 5. Themethod as claimed in claim 4, wherein said diffusions are carried outfor sufficient time to establish the concentration of oppositeconductivity impurities in said first and second zones within the rangeof 1014 - 1016 atoms/cc and 1017 - 1020 atoms/cc, respectively.
 6. Themethod as claimed in claim 4, wherein said first stage diffusion iscarried out so as to extend beyond the periphery of said second stagediffusion on said surface by a distance of between 0.2 mils and 1 mil.7. In the construction of dielectrically isolated, diffused, planarintegrated circuitry wherein discrete bodies of single crystalsemiconductive material are embedded in a polycrystalline or amorphousmatrix with an insulating oxide layer therebetween, and including thediffusion of one conductivity type material into a body ofsemiconductive material having a concentration of the oppositeconductivity type impurities of less than about 1015 atoms/cc, therebyto form a PN junction within said body, followed by establishing anoxide film on a major surface of said body and connection of metallicleads overlying said film to opposite sides of said junction, theimprovement comprising diffusing said one conductivity type impurity ininterchangeable first and second stages, said first stage being carriedout for a time sufficient to establish an impurity concentration of lessthan about 1016 atoms/cc, which establishes said junction, said firststage diffusion extending into said oxide layer beneath at least thelead to be connected to that side of said junction, said second stagediffusion being within an area entirely surrounded on said surface bysaid first stage diffusion and being carried out for a time sufficientto establish an average impurity concentration of said one conductivitytype of from two to four orders of magnitude greater than in said firststage diffusion.
 8. The method as claimed in claim 7, wherein the bulkconcentration of first conductivity type impurities in said material is1013 - 1015 atoms/cc, and said first and second stage diffusions arecarried out for sufficient time to establish average surfaceconcentrations of said one conductivity-type impurity of 1014 - 1016atoms/cc and 1017 - 1010 atoms/cc, respectively.
 9. The method asclaimed in claim 7, wherein said first stage diffusion is carried out soas to extend beyond the periphery of said second stage diffusion on saidsurface by a distance of at least 0.2 mils, and extends beneath saidlead and into said dielectric isolation material at least 0.5 mils.